Strange Port Behaviour

[slagernate]

Somehow this port, which was messing with my LVS (VDD was shorted to an NFET gate at the other end of the layout 🤷 ) was added in my layout. Near the end of my layout.mag:

rlabel polycont 2443 -1303 2443 -1303 0 G
port 3 nsew

I suspect this was created when I copied/duplicated a parameterized fet (perhaps it was made a port by me accidentally selecting too large of a box when converting my actual labels to ports).

I deleted this line (and re-numbered my ports) and all is well now.