[spectec] Fix printing of some vector conversion ops

Author: rossberg

document/core/binary/instructions.rst

@@ -384,31 +384,6 @@ $${grammar: {
 
 $${grammar: {Binstr/vec-cvt}}
 
-.. math::
-   \begin{array}{llclll}
-   \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
-     \hex{FD}~~256{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDSWIZZLE \\ &&|&
-     \hex{FD}~~257{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDTRUNC\K{\_f32x4\_s} \\ &&|&
-     \hex{FD}~~258{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDTRUNC\K{\_f32x4\_u} \\ &&|&
-     \hex{FD}~~259{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDTRUNC\K{\_f32x4\_s\_zero} \\ &&|&
-     \hex{FD}~~260{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDTRUNC\K{\_f32x4\_u\_zero} \\ &&|&
-     \hex{FD}~~261{:}\Bu32 &\Rightarrow& \F32X4.\VRELAXEDMADD \\ &&|&
-     \hex{FD}~~262{:}\Bu32 &\Rightarrow& \F32X4.\VRELAXEDNMADD \\ &&|&
-     \hex{FD}~~263{:}\Bu32 &\Rightarrow& \F64X2.\VRELAXEDMADD \\ &&|&
-     \hex{FD}~~264{:}\Bu32 &\Rightarrow& \F64X2.\VRELAXEDNMADD \\ &&|&
-     \hex{FD}~~265{:}\Bu32 &\Rightarrow& \I8X16.\VRELAXEDLANESELECT \\ &&|&
-     \hex{FD}~~266{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDLANESELECT \\ &&|&
-     \hex{FD}~~267{:}\Bu32 &\Rightarrow& \I32X4.\VRELAXEDLANESELECT \\ &&|&
-     \hex{FD}~~268{:}\Bu32 &\Rightarrow& \I64X2.\VRELAXEDLANESELECT \\ &&|&
-     \hex{FD}~~269{:}\Bu32 &\Rightarrow& \F32X4.\VRELAXEDMIN \\ &&|&
-     \hex{FD}~~270{:}\Bu32 &\Rightarrow& \F32X4.\VRELAXEDMAX \\ &&|&
-     \hex{FD}~~271{:}\Bu32 &\Rightarrow& \F64X2.\VRELAXEDMIN \\ &&|&
-     \hex{FD}~~272{:}\Bu32 &\Rightarrow& \F64X2.\VRELAXEDMAX \\ &&|&
-     \hex{FD}~~273{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDQ15MULR\K{\_s} \\ &&|&
-     \hex{FD}~~274{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDDOT\K{\_i8x16\_i7x16\_s} \\ &&|&
-     \hex{FD}~~275{:}\Bu32 &\Rightarrow& \I16X8.\VRELAXEDDOT\K{\_i8x16\_i7x16\_add\_s} \\
-   \end{array}
-
 
 .. index:: expression
    pair: binary format; expression

specification/wasm-3.0/1.3-syntax.instructions.spectec

@@ -165,14 +165,14 @@ syntax vcvtop__(Jnn_1 X M_1, Jnn_2 X M_2) =
   | EXTEND half sx hint(show EXTEND#_#%#_#%)
     -- if $lsizenn2(Jnn_2) = $(2 * $lsizenn1(Jnn_1))
 syntax vcvtop__(Jnn_1 X M_1, Fnn_2 X M_2) =
-  | CONVERT half? sx hint(show CONVERT#_#%#_#%) hint(show CONVERT#_#%)
+  | CONVERT half? sx hint(show CONVERT#_#%) hint(show CONVERT#_#%#_#%)
     -- if $sizenn2(Fnn_2) = $lsizenn1(Jnn_1) = `32 /\ half? = eps
        \/ $sizenn2(Fnn_2) = $(2 * $lsizenn1(Jnn_1)) /\ half? = LOW
 syntax vcvtop__(Fnn_1 X M_1, Jnn_2 X M_2) =
-  | TRUNC_SAT sx zero? hint(show TRUNC_SAT#_#%#_#%) hint(show TRUNC_SAT#_#%)
+  | TRUNC_SAT sx zero? hint(show TRUNC_SAT#_#%) hint(show TRUNC_SAT#_#%#_#%)
     -- if $sizenn1(Fnn_1) = $lsizenn2(Jnn_2) = `32 /\ zero? = eps
        \/ $sizenn1(Fnn_1) = $(2 * $lsizenn2(Jnn_2)) /\ zero? = ZERO
-  | RELAXED_TRUNC sx zero? hint(show RELAXED_TRUNC#_#%#_#%) hint(show RELAXED_TRUNC#_#%)
+  | RELAXED_TRUNC sx zero? hint(show RELAXED_TRUNC#_#%) hint(show RELAXED_TRUNC#_#%#_#%)
     -- if $sizenn1(Fnn_1) = $lsizenn2(Jnn_2) = `32 /\ zero? = eps
        \/ $sizenn1(Fnn_1) = $(2 * $lsizenn2(Jnn_2)) /\ zero? = ZERO
 syntax vcvtop__(Fnn_1 X M_1, Fnn_2 X M_2) =