Pcie30PhyLib: Assorted fixes

- Clean up dead code.

- Perform init only once. This fixes an issue in bifurcation mode where
PCIe 3x2 init would reset the PHY, forcing the previously configured
PCIe 3x4 link to restart at the lowest speed.

- Set PHP_GRF_PCIESEL_CON to fix routing of PCIe3x1 controllers to the
PCIe 3 PHY instead of the Combo PHY.

- Wait for sram_init_done (does not seem necessary since
sram_bypass=0x1, but just follow suit with the BSP code).

Signed-off-by: Mario Bălănică <[email protected]>

Author: mariobalanica

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.c

@@ -5,6 +5,7 @@
  *  Copyright (c) 2023, David Gwynne <[email protected]>
  *  Copyright (c) 2023, Jared McNeill <[email protected]>
  *  Copyright (c) 2023, Molly Sophia <[email protected]>
+ *  Copyright (c) 2025, Mario Bălănică <[email protected]>
  *
  *  SPDX-License-Identifier: BSD-2-Clause-Patent
  *
@@ -18,100 +19,85 @@
 #include <Library/CruLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 #include <Library/PcdLib.h>
+#include <VarStoreData.h>
 
-#define PCIE30_PHY_GRF  0xfd5b8000
-/* PCIEPHY_GRF */
-#define GRF_PCIE30_PHY_CON(n)       (PCIE30_PHY_GRF + 0x0000 + (n) * 0x4)         /* 0 .. 9 */
-#define GRF_PCIE30_PHY_STATUS(n)    (PCIE30_PHY_GRF + 0x0080 + (n) * 0x4)         /* 0 .. 2 */
-#define GRF_PCIE30_PHY_PRT0_CON(n)  (PCIE30_PHY_GRF + 0x0100 + (n) * 0x4)         /* 0 .. 39 */
-/* CON1 and CON9 */
-#define GRF_PCIE30PHY_DA_OCM_MASK  BIT15
-#define GRF_PCIE30PHY_DA_OCM       BIT15
-/* CON5 */
-#define GRF_PCIE30PHY_LANE0_LINK_NUM_SHIFT  0
-#define GRF_PCIE30PHY_LANE0_LINK_NUM_MASK   (0xfU << GRF_PCIE30PHY_LANE0_LINK_NUM_SHIFT)
-/* CON6 */
-#define GRF_PCIE30PHY_LANE1_LINK_NUM_SHIFT  0
-#define GRF_PCIE30PHY_LANE1_LINK_NUM_MASK   (0xfU << GRF_PCIE30PHY_LANE1_LINK_NUM_SHIFT)
-
-/* STATUS0 */
-#define GRF_PCIE30PHY_SRAM_INIT_DONE  BIT14
-
-#define SOFTRST_INDEX  27
-#define SOFTRST_BIT    14
-
-STATIC
-VOID
-GrfUpdateRegister (
-  IN EFI_PHYSICAL_ADDRESS  Reg,
-  IN UINT32                Mask,
-  IN UINT32                Val
-  )
-{
-  ASSERT ((Mask & ~0xFFFF) == 0);
-  ASSERT ((Val & ~0xFFFF) == 0);
-  ASSERT ((Mask & Val) == Val);
+#define PHP_GRF_BASE       0xfd5b0000
+#define PCIE3PHY_GRF_BASE  0xfd5b8000
 
-  MmioWrite32 (Reg, (Mask << 16) | Val);
-}
+/* PHP_GRF */
+#define PHP_GRF_PCIESEL_CON  0x100
+
+/* PCIE3PHY_GRF */
+#define PCIE3PHY_GRF_CMN_CON0      0x0
+#define PCIE3PHY_GRF_PHY0_STATUS1  0x904
+#define PCIE3PHY_GRF_PHY1_STATUS1  0xa04
+#define PCIE3PHY_SRAM_INIT_DONE(reg)  ((reg & BIT0) != 0)
+
+STATIC EFI_STATUS  mInitStatus = EFI_NOT_READY;
 
 EFI_STATUS
 Pcie30PhyInit (
   VOID
   )
 {
-  // UINTN Retry;
+  UINT8   Mode;
+  UINT32  Reg;
+  UINTN   Retry;
 
-  DEBUG ((DEBUG_INFO, "PCIe30: PHY init\n"));
-  DEBUG ((DEBUG_INFO, "PCIe30: PHY mode %d\n", PcdGet8 (PcdPcie30PhyMode)));
+  if (mInitStatus != EFI_NOT_READY) {
+    return mInitStatus;
+  }
 
-  // MicroSecondDelay(100000);
+  Mode = PcdGet8 (PcdPcie30PhyMode);
 
-  /* Disable power domain */
+  DEBUG ((DEBUG_INFO, "PCIe30: PHY init\n"));
+  DEBUG ((DEBUG_INFO, "PCIe30: PHY mode %d\n", Mode));
+
+  /* Enable power domain */
   MmioWrite32 (0xFD8D8150, 0x1 << 23 | 0x1 << 21);  // PD_PCIE & PD_PHP
 
-  /* Phy mode: from pcd Pcie30PhyMode */
-  MmioWrite32 (GRF_PCIE30_PHY_CON (0), (0x7 << 16) | PcdGet8 (PcdPcie30PhyMode));
+  /* Phy mode */
+  Reg = Mode;
+  MmioWrite32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_CMN_CON0, (0x7 << 16) | Reg);
+
+  /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
+  Reg &= 0x3;
+  if (Reg) {
+    MmioWrite32 (PHP_GRF_BASE + PHP_GRF_PCIESEL_CON, (0x3 << 16) | Reg);
+  }
 
+  /* Assert PHY Reset */
   MmioWrite32 (0xFD7C8A00, (0x1 << 10) | (0x1 << 26));
+  MicroSecondDelay (1);
 
   /* Deassert PCIe PMA output clamp mode */
-  MmioWrite32 (GRF_PCIE30_PHY_CON (0), (0x1 << 8) | (0x1 << 24));
+  MmioWrite32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_CMN_CON0, (0x1 << 8) | (0x1 << 24));
 
   /* Deassert PHY Reset */
   MmioWrite32 (0xFD7C8A00, (0x1 << 26));
 
-  // /* Enable clocks */
-  // PmuCruEnableClock (2, 13);
-  // PmuCruEnableClock (2, 14);
-  // CruEnableClock (33, 8);
-
-  // /* Assert reset */
-  // CruAssertSoftReset (SOFTRST_INDEX, SOFTRST_BIT);
-  // gBS->Stall (1000);
+  for (Retry = 500; Retry > 0; Retry--) {
+    Reg = MmioRead32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_PHY0_STATUS1);
+    if (Mode == PCIE30_PHY_MODE_AGGREGATION) {
+      Reg &= MmioRead32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_PHY1_STATUS1);
+    }
 
-  // MicroSecondDelay (1);
+    if (PCIE3PHY_SRAM_INIT_DONE (Reg)) {
+      break;
+    }
 
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (9), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM);
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (5), GRF_PCIE30PHY_LANE0_LINK_NUM_MASK, PCIE30PHY_LANE0_LINK_NUM);
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (6), GRF_PCIE30PHY_LANE1_LINK_NUM_MASK, PCIE30PHY_LANE1_LINK_NUM);
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (1), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM);
+    MicroSecondDelay (100);
+  }
 
-  // /* De-assert reset */
-  // CruDeassertSoftReset (SOFTRST_INDEX, SOFTRST_BIT);
-
-  // for (Retry = 500; Retry > 0; Retry--) {
-  //     MicroSecondDelay (100);
-
-  //     if ((MmioRead32 (GRF_PCIE30_PHY_STATUS (0)) & GRF_PCIE30PHY_SRAM_INIT_DONE) != 0) {
-  //         break;
-  //     }
-  // }
-  // if (Retry == 0) {
-  //     DEBUG ((DEBUG_WARN, "PCIe30: Failed to enable PCIe 3.0 PHY\n"));
-  //     return EFI_TIMEOUT;
-  // }
+  if (Retry == 0) {
+    DEBUG ((DEBUG_WARN, "PCIe30: PHY init failed\n"));
+    mInitStatus = EFI_TIMEOUT;
+    goto Exit;
+  }
 
   DEBUG ((DEBUG_INFO, "PCIe30: PHY init complete\n"));
-  return EFI_SUCCESS;
+  mInitStatus = EFI_SUCCESS;
+
+Exit:
+  return mInitStatus;
 }

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c

@@ -3,7 +3,7 @@
   Copyright 2017, 2020 NXP
   Copyright 2021-2023, Jared McNeill <[email protected]>
   Copyright 2023, Molly Sophia <[email protected]>
-  Copyright (c) 2023-2024, Mario Bălănică <[email protected]>
+  Copyright (c) 2023-2025, Mario Bălănică <[email protected]>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -577,6 +577,7 @@ InitializePciHost (
   EFI_PHYSICAL_ADDRESS  ApbBase  = PCIE_APB_BASE (Segment);
   EFI_PHYSICAL_ADDRESS  DbiBase  = PCIE_DBI_BASE (Segment);
   EFI_PHYSICAL_ADDRESS  PcieBase = PCIE_CFG_BASE (Segment);
+  EFI_STATUS            Status;
   UINTN                 Retry;
   UINT32                LinkSpeed;
   UINT32                LinkWidth;
@@ -622,7 +623,10 @@ InitializePciHost (
 
   if ((Segment == PCIE_SEGMENT_PCIE30X4) || (Segment == PCIE_SEGMENT_PCIE30X2)) {
     /* Configure PCIe 3.0 PHY */
-    Pcie30PhyInit ();
+    Status = Pcie30PhyInit ();
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
   }
 
   /* Combo PHY for PCIe 2.0 is configured earlier by RK3588Dxe */