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Re_RISCV

RISC-V based cpu processor(PipelineProcessor)

IcarusVerilogシミュレーション

コンパイル(systemVerilog)

 iverilog -g 2012 <module file>.v <testbench>.v

オプション:https://tanakatarou.tech/627/

シミュレーション

vvp a.out

シミュレーション(波形)

gtkwave <シミュレーション時に出力されるファイル>.vcd

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RISC-V based cpu processor

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