This repository contains the benchmarks of IWLS 2025 Programming Contest and the circuits produced by the participants.
The goal of the contest was to synthesize AIGs with the minimal number of two-input and-nodes (AIGs) for two sets of completely-specified multi-output Boolean functions represented using truth tables. The AIGs for both sets of benchmarks were submited in binary AIGER format. For the detailed information about the rules and evaluation criteria, please refer to this year's contest description.
The contest was organized by Alan Mishchenko and Alessandro Tempia Calvino (IWLS 2025 Contest Chairs)
The benchmarks available in this repository include 200 functions.
The first set of 100 functions is the same set that appeared in the IWLS 2022 competition. The second set of 100 functions are new functions generated specifically for this contest.
Please refer to the results presentation for the details on the benchmarks.
Despite the original intention to release the Verilog source code of the benchmarks, it was decided to postpone the release, because the same test-cases may be used again in future competitions.
Please refer to the results presentation for the details on the participants.
With the participants' permission, the circuits submitted to the contest can be found here.
Please refer to the results presentation for the details on the winners.
The winner presentations can be found here.
Congratulations to the winners!