WARNING: THIS SITE IS A MIRROR OF GITHUB.COM / IT CANNOT LOGIN OR REGISTER ACCOUNTS / THE CONTENTS ARE PROVIDED AS-IS / THIS SITE ASSUMES NO RESPONSIBILITY FOR ANY DISPLAYED CONTENT OR LINKS / IF YOU FOUND SOMETHING MAY NOT GOOD FOR EVERYONE, CONTACT ADMIN AT ilovescratch@foxmail.com
Skip to content
View celuk's full-sized avatar

Highlights

  • Pro

Organizations

@kasirgalabs @HYSUM-TOBBETU @Bitirmeceler-4 @KASIRGA-KIZIL

Block or report celuk

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. KASIRGA-KIZIL/tekno-kizil KASIRGA-KIZIL/tekno-kizil Public

    KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

    Verilog 155 11

  2. kasirgalabs/ERIC kasirgalabs/ERIC Public

    Compiler Level RISC-V Encryption Tool https://ieeexplore.ieee.org/document/9833625

    C++ 11 1

  3. tpcds-postgres tpcds-postgres Public

    TPC-DS Generation, Execution and Analyzer for Postgres

    C 20 5

  4. HYSUM-TOBBETU/AES-Encryption-Verilog-Pipelined-Implementation-128bit HYSUM-TOBBETU/AES-Encryption-Verilog-Pipelined-Implementation-128bit Public

    Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog

    Verilog 11

  5. wallace-multiplier-cmos-vlsi wallace-multiplier-cmos-vlsi Public

    8bit x 8bit Signed Wallace Tree Multiplier 600nm CMOS VLSI Design

    Verilog 2

  6. Bitirmeceler-4/iki-boyutlu-top-stabilizasyon-platformu Bitirmeceler-4/iki-boyutlu-top-stabilizasyon-platformu Public

    Python 1