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A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

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powerful heightened yielded Logic Synthesis (phyLS)

phyLS is based on the mockturtle and the abc, it can optimize different logics attributes. Currently, it supports mockturtle format(AIG, MIG, XAG, XMG) and abc format(AIG,GIA) based optimization.

Read the documentation here.

The documentation generated by deepwiki for phyLS.

Requirements

A modern compiler is required to build the libraries. Compiled successfully with Clang 6.0.1, Clang 12.0.0, GCC 7.3.0, and GCC 8.2.0.

How to Compile

git clone --recursive https://github.com/panhomyoung/phyLS.git
cd phyLS
mkdir build
cd build
cmake ..
make
./bin/phyLS

Citing this Work

If you use this software in any published work, we would appreciate a citation! Please use the following references:

  1. Paper describing this work has been received in Frontiers of Computer Science(FCS) special column “Code & Data”.
@article{hongyang2025phyls,
  title={PhyLS: An AI-driven Physically Aware Synthesis},
  author={ Hongyang PAN, Cunqing LAN, Zhiang WANG, Keren ZHU},
  journal={Frontiers of Computer Science},
  pages={1105--1110},
  year={2025},
  doi={10.1007/s11704-025-51861-4}
}

If you like the tools, please give us a star on our GitHub repos!

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A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

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